A Tale of Two Sides of Wafer: Physical Implementation and Block-Level PPA on Flip FET with Dual-sided Signals

Abstract

This paper presents the Flip FET (FFET), a novel transistor architecture that uses 3D stacking and a fully functional wafer backside to enable dual-sided standard cell designs and signal routing. Utilizing a comprehensive physical evaluation framework on a 32-bit RISC-V core, the FFET demonstrated substantial Power-Performance-Area (PPA) gains over conventional CFET technology, including a 23.3% reduction in core area and 25.0% higher frequency. Further optimization using dual-sided signals provided an additional 10.6% frequency increase, validating FFET as a highly efficient path for next-generation logic scaling.

Report

Analysis of Flip FET (FFET) Implementation and PPA

Key Highlights

• Novel Architecture: The FFET is a new transistor design combining 3D transistor stacking with a fully functional wafer backside, facilitating symmetric dual-sided standard cell design.
• PPA Superiority over CFET: Compared to CFET (with single-sided signals), FFET (with single-sided signals) achieved significant improvements in a 32-bit RISC-V core implementation:
  • 23.3% core area reduction (post-P&R).
  • 25.0% higher frequency at the same utilization.
  • 11.9% lower power at the same utilization.
• Cell Area Scaling: FFET inherently delivers around 12.5% cell area scaling compared to other stacked transistor technologies like CFET.
• Dual-Sided Signal Benefit: Leveraging dual-sided signal routing, FFET realized an additional 10.6% frequency gain by optimizing the allocation of cell input pins and BEOL layers.
• Cost Efficiency Potential: The architecture maintains high routability and power efficiency even when the number of routing layers is drastically reduced (from 12 to 5 layers per side), suggesting significant cost-friendly design space.

Technical Details

• FFET Design Principle: FFET uses symmetric dual-sided standard cells with dual-sided pins, enabling signal routing on both the frontside and the fully functional wafer backside.
• Evaluation Framework: The study developed a comprehensive FFET evaluation framework, crucial components of which were the capabilities for dual-sided routing and dual-sided RC extraction (Resistance-Capacitance modeling).
• Benchmark: The effectiveness of the physical implementation flow was demonstrated using a high-level design implementation of a 32-bit RISC-V core.
• Performance Metrics: When targeting the same core area, the FFET achieved a 16.0% higher frequency compared to CFET with single-sided signals.
• Optimization Strategy: The additional 10.6% frequency gain achieved through dual-sided signals was realized specifically by optimizing the input pin density and the allocation of the Back-End-of-Line (BEOL) routing layer number on each wafer side.

Implications

• Solving Scaling Limits: This work provides a tangible solution to the challenge of conventional logic device scaling, utilizing 3D stacking and backside routing to dramatically extend design space for signals and power delivery.
• Advancement of RISC-V Implementation: Using a 32-bit RISC-V core as the test vehicle demonstrates the immediate applicability and massive PPA benefits this technology can bring to modern, high-performance, open-source hardware designs.
• Routability and Density Breakthrough: The introduction of dual-sided signal routing fundamentally addresses congestion issues in high-density integrated circuits, leading to better routability and enabling tighter integration than traditional single-sided approaches.
• Future Manufacturing Cost Reduction: The finding that FFET maintains PPA even with fewer metal layers (reducing from 12 to 5 per side) suggests that future chips built on this architecture could significantly reduce manufacturing complexity and cost without sacrificing performance.