A Survey on RISC-V Security: Hardware and Architecture

Abstract

This paper presents the first comprehensive survey of security solutions for the open RISC-V Instruction Set Architecture (ISA), addressing a critical research gap in the rapidly evolving IoT landscape. It analyzes representative security mechanisms implemented at the hardware and architectural levels, aimed at establishing a robust Root of Trust (RoT). The survey summarizes current research and provides predictions for future development directions to inspire researchers and accelerate secure RISC-V adoption.

Report

Key Highlights

• Filling a Research Gap: The survey addresses the lack of a comprehensive academic overview of ongoing RISC-V security research projects.
• RISC-V as Mainstream: It acknowledges the transition of RISC-V from an emerging standard to a mainstream alternative, especially in the Internet of Things (IoT) space, traditionally dominated by Arm.
• Core Security Goals: Security solutions surveyed are primarily focused on achieving a Root of Trust (RoT) and ensuring that sensitive information on RISC-V devices is neither tampered with nor leaked.
• Scope: The analysis covers representative security mechanisms implemented at the hardware and architectural levels.
• Future Prediction: The paper concludes by forecasting future research and development directions to guide the RISC-V community.

Technical Details

• Target Architecture: The analysis is focused exclusively on the free and open RISC-V ISA standard.
• Application Domain: Embedded processors and smart IoT devices are identified as the primary use case where security challenges are most acute.
• Focus Area: The specific technical focus is on mechanisms designed into the core architecture and underlying hardware to mitigate foreseeable security threats.
• Security Mechanisms: The ultimate goal of the reviewed mechanisms is data security, user privacy protection, and ensuring system integrity against tampering.

Implications

• Accelerated Adoption: By synthesizing current security efforts, the paper provides validation and guidance, fostering trust in the RISC-V ISA for security-sensitive applications, thus accelerating its transition to mainstream use in IoT.
• Strategic Guidance: The identification of future research directions helps guide academic efforts and industry investments towards necessary long-term security features for the open ISA.
• Foundational Resource: The survey serves as a vital reference point for developers and researchers, helping them to quickly understand the state-of-the-art in RISC-V hardware and architectural security design.
• Competitiveness: The proactive study and summary of security solutions help ensure that RISC-V remains competitive against established proprietary ISAs (like Arm) by addressing crucial security and privacy challenges early in its lifecycle.