A Soft Processor Overlay with Tightly-coupled FPGA Accelerator

Abstract

This paper presents an open-source soft processor designed for tight integration within an FPGA overlay framework to facilitate full application acceleration. Leveraging the RISC-V instruction set and a 4-stage pipeline, the design balances resource consumption, performance, and portability across various FPGA platforms. The resulting architecture achieves performance comparable to hardware-only accelerators while providing essential run-time flexibility for integrated software-hardware applications.

Report

Structured Report: A Soft Processor Overlay with Tightly-coupled FPGA Accelerator

Key Highlights

• Integrated Overlay Framework: The core innovation is an open-source soft processor designed specifically to collaborate closely with coarse-grained reconfigurable FPGA accelerators within a unified overlay architecture.
• RISC-V Foundation: The processor utilizes the RISC-V Instruction Set Architecture (ISA), chosen primarily for its openness and portability, promoting generic implementation across various vendors.
• High Efficiency and Flexibility: The integrated software-hardware applications achieve performance comparable to highly optimized hardware-only solutions, a key benefit being the added run-time flexibility.
• Portability: The design is generically implemented, supporting synthesis on both low-end and high-performance FPGA families from different vendors.

Technical Details

• Architecture Type: FPGA Overlay (Coarse-Grained Reconfigurable Architecture).
• Processor Design: A soft processor designed for tight-coupling (Tightly-coupled FPGA Accelerator).
• Pipeline Stage Count: The processor employs a 4-stage pipeline, optimized to balance resource consumption and execution performance when deployed on FPGAs.
• ISA: RISC-V.
• Performance Metric: Demonstrated highest operating frequency achieved was 268.67MHz, with resource consumption comparable to existing RISC-V implementations.
• Implementation Goal: Designed to promote portability and compatibility across differing FPGA platforms.

Implications

• Advancing Heterogeneous Computing: This work provides a scalable, efficient blueprint for integrating flexible software control (via the soft processor) directly alongside high-speed hardware acceleration (FPGA fabric) without sacrificing performance.
• Boosting RISC-V Ecosystem on FPGAs: Choosing RISC-V reinforces its role as the dominant open standard for customized embedded processors, providing a portable, open-source CPU core crucial for complex acceleration systems.
• Improving Developer Productivity: By providing the solution within an overlay framework, designers benefit from increased ease of configuration and a standardized environment, simplifying the development of software-hardware co-designed applications.
• Flexibility in the Data Center/Edge: The combination of high performance and run-time flexibility is critical for applications that require dynamic reconfiguration or adaptation based on changing inputs, pushing the capabilities of reconfigurable computing.