A RISC-V SystemC-TLM simulator

Abstract

This work presents a SystemC-TLM based simulator for a RISC-V microcontroller, prioritizing simplicity and expandability for System-on-Chip (SoC) development. It integrates a full RISC-V Instruction Set Simulator (ISS) supporting key ISA extensions, encapsulated in a TLM-2 wrapper for standardized communication. The simulator is validated by successfully executing the riscv-compliance suite and is conveniently published as a Docker image alongside a dedicated FreeRTOS port.

Report

Key Highlights

• SystemC-TLM Standard: The simulator is built using SystemC and Transaction-Level Modeling (TLM-2) standards, ensuring compatibility and modularity in SoC design flows.
• Full ISA Support: It features a complete RISC-V Instruction Set Simulator (ISS) supporting the base ISA plus crucial extensions.
• Validation: The simulator is verified to correctly execute the industry-standard riscv-compliance test suite.
• Ease of Use: It supports standard C libraries and compilation tools without modification, enabling rapid software development.
• Accessibility: The entire simulator is distributed as a pre-configured Docker image, simplifying installation and deployment for developers.
• OS Support: A port of FreeRTOS version 10.2.1 for the simulated SoC is publicly released.

Technical Details

• Modeling Framework: SystemC using the TLM-2 standard for communication between components.
• Core Component: A robust RISC-V ISS provides the processor functionality.
• Supported ISA Extensions: The ISS supports the M (Multiplication/Division), A (Atomic operations), C (Compressed instructions), Zicsr (Control and Status Register access), and Zifencei (Instruction-Fetch Fence) extensions.
• Architecture: The ISS is wrapped in a TLM-2 wrapper, allowing it to interface directly with any other TLM-2 compatible module (e.g., memory, peripherals).
• System Components: The solution includes a basic set of peripherals required to complete a functional microcontroller SoC simulation.

Implications

• Accelerated Development: By providing a reliable, standardized simulation environment (SystemC-TLM), the tool allows hardware and software teams to concurrently develop and debug embedded software for RISC-V targets before physical hardware is available.
• Standardization and Interoperability: Adherence to the TLM-2 standard promotes modularity, enabling easier integration of third-party IP cores and peripherals into the simulated SoC structure.
• Lowered Entry Barrier: The distribution as a Docker image drastically simplifies setup, making RISC-V simulation more accessible to researchers, hobbyists, and commercial developers globally.
• Software Ecosystem Growth: The successful porting and publication of FreeRTOS demonstrate the simulator's maturity and its ability to host real-world operating systems, significantly bolstering the RISC-V embedded software ecosystem.