A RISC-V Simulator and Benchmark Suite for Designing and Evaluating Vector Architectures

Abstract

Vector architecture research currently suffers from a critical lack of flexible simulation tools and standardized benchmark suites, particularly within platforms like gem5. This work introduces a parameterizable RISC-V Vector Architecture model by extending the gem5 simulator, enabling designers to test different architectural approaches. Furthermore, the paper presents a novel Vectorized Benchmark Suite of seven data-parallel applications categorized to stress various vector components, covering targets from short-vector embedded systems to large-vector High-Performance Computing.

Report

Key Highlights

• Tool Gap Addressed: The primary motivation is the recognized lack of flexible simulation tools for vector architectures, specifically noting that the leading gem5 platform lacks a usable vector architecture model.
• Simulator Extension: A parameterizable RISC-V Vector Architecture model has been integrated into the gem5 simulator, allowing designers to customize and evaluate different vector design approaches.
• Novel Benchmark Suite: A new Vectorized Benchmark Suite is introduced, consisting of seven data-parallel applications from different domains.
• Comprehensive Coverage: The benchmark suite is designed to test varying usage scenarios, including designs optimized for short vectors (embedded systems) and those requiring large vectors (High-Performance Computing or HPC).

Technical Details

• Base Platform: The simulation tools are built upon an extension of the established gem5 simulator.
• Instruction Set: The platform supports the execution of RISC-V Vector instructions.
• Customization: The vector architecture model is parameterizable, allowing researchers to adjust parameters relevant to the target application domain.
• Benchmark Classification: Applications within the suite are classified based on the specific architectural modules they stress (e.g., load/store units, arithmetic units, vector registers).
• Experimental Use: The work includes a study demonstrating the execution of the Vectorized Benchmark Suite on the newly developed gem5-based vector architecture model.

Implications

• Standardization of Research: By providing a common, flexible simulation platform and a standardized benchmark suite, the work significantly lowers the entry barrier for vector architecture research and facilitates the objective comparison of novel designs.
• Accelerated Development: Researchers no longer need to spend significant time developing foundational simulation platforms, allowing them to focus their efforts on innovative architectural concepts.
• Driving RISC-V Vector Growth: The tools directly support the optimization and robust testing of the RISC-V Vector Extension (RVV), crucial for advancing the adoption of RISC-V in high-performance and data-intensive computing fields.
• Domain-Specific Optimization: The benchmark suite enables architecture designers to fine-tune their implementations specifically for embedded systems (e.g., IoT, mobile) or HPC applications, which require fundamentally different vector lengths and capabilities.