A RISC-V MCU with adaptive reverse body bias and ultra-low-power retention mode in 22 nm FD-SOI

A RISC-V MCU with adaptive reverse body bias and ultra-low-power retention mode in 22 nm FD-SOI

Abstract

This paper introduces a highly energy-efficient 32-bit RISC-V MCU fabricated in 22 nm FD-SOI technology, utilizing adaptive reverse body biasing (RBB) to achieve ultra-low leakage current across the full industrial temperature range. The design incorporates custom SRAM macros with a dedicated retention mode, allowing the device to surpass state-of-the-art performance in deep-sleep power consumption. While active power matches SOTA at 4.8 uW/MHz, the combination of FD-SOI and RBB significantly enhances robustness and standby efficiency for demanding IoT applications.

Report

Key Highlights

  • Ultra-Low Leakage Achieved: The design focuses heavily on minimizing leakage current, particularly at high temperatures, through advanced techniques.
  • State-of-the-Art Efficiency: The MCU matches the current SOTA performance in active mode, demonstrating an efficiency of 4.8 uW/MHz at 50 MHz.
  • Retention Mode Excellence: The device surpasses SOTA figures in its ultra-low-power retention mode, critical for battery-powered, intermittently active systems.
  • Robustness Verified: The chip's operation was successfully measured and verified across the full industrial temperature range, spanning from -40 °C to 125 °C.

Technical Details

  • Core Architecture: 32-bit RISC-V microprocessor unit (MCU).
  • Fabrication Process: 22 nm Fully Depleted Silicon On Insulator (FD-SOI).
  • Key Power Management Technique: Adaptive Reverse Body Biasing (RBB), applied via an RBB-aware sign-off approach, to dynamically control leakage and threshold voltage.
  • Memory Implementation: Custom SRAM macros specifically designed to support an ultra-low-power retention mode.
  • Active Performance Metric: 4.8 uW / MHz efficiency when operating at 50 MHz.
  • Optimization: Includes a low-power optimized physical implementation strategy.

Implications

  • RISC-V Enablement: This work validates the feasibility and competitive energy efficiency of RISC-V cores within advanced, specialized process nodes like 22 nm FD-SOI.
  • IoT and Edge Computing: The superior performance in retention mode and ultra-low leakage are vital for battery-operated IoT sensors, wearables, and edge devices that spend most of their time in standby.
  • Reliability in Harsh Environments: The demonstrated robustness across the extreme industrial temperature range (-40 °C to 125 °C) makes this technology highly suitable for automotive, industrial control, and specialized outdoor applications where temperature stability is paramount.
  • FD-SOI Advantage: It showcases the benefit of FD-SOI technology, particularly its ability to utilize body biasing for dynamic performance and power optimization, providing a significant edge over bulk CMOS processes in low-power domains.
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