A Novel Compaction Approach for SBST Test Programs

Abstract

This work introduces a novel compaction strategy designed to significantly reduce the size and duration of Self-Test Library (STL) programs used for in-field testing of safety-critical processors. The approach analyzes the interaction between an instruction's micro-architectural operation and its fault propagation capacity, minimizing the required fault simulations to just one. Validated on a RISC-V processor, this method achieved test program length and duration reductions of up to 93.9% and 95%, respectively, with minimal impact on fault coverage.

Report

Key Highlights

• Target Domain: Addresses the crucial constraints (size and duration) of Self-Test Libraries (STLs) for in-field testing in safety-critical systems (e.g., aerospace, automotive).
• Core Innovation: A novel compaction approach for functional test programs within STLs.
• Efficiency Gain: The method dramatically simplifies the verification process, requiring only a single fault simulation.
• Performance Metrics: Achieved substantial reductions in both test length (up to 93.9%) and test duration (up to 95%).
• Validation: The compaction strategy was validated using a RISC-V processor implementation and various test generation strategies.

Technical Details

• Methodology: The compaction process is based on analyzing the test program through logic simulation.
• Compaction Criterion: The technique evaluates two specific aspects of each instruction: its micro-architectural operation and its subsequent capacity to propagate fault effects onto an observable output.
• Fault Simulation Reduction: By integrating the analysis of propagation capacity, the need for extensive traditional fault simulations is virtually eliminated, reducing the requirement to only one instance.
• Application: Applicable to test programs generated via diverse generation strategies.

Implications

• Enabling Safety-Critical Adoption: For industries like automotive and aerospace where test program size and speed are heavily constrained, this breakthrough makes Self-Built Self-Test (SBST) more feasible and efficient, thus improving overall system reliability.
• Resource Efficiency: By shrinking test program size by over 90%, the method frees up significant memory resources in resource-constrained embedded systems, a common deployment environment for RISC-V cores.
• Strengthening RISC-V Ecosystem: Validation of this highly efficient testing and compaction method on RISC-V hardware enhances the credibility of the architecture for deployment in high-assurance and functional safety applications, accelerating its adoption outside general compute.