A Heterogeneous RISC-V based SoC for Secure Nano-UAV Navigation

Abstract

The Shaheen SoC is a 9mm² heterogeneous RISC-V based processor designed to enable secure and autonomous navigation for energy-constrained nano-UAVs, addressing the need for advanced ML capabilities and secure operating system co-existence. Implemented in 22nm FDX technology, it pairs a Linux-capable RV64 core featuring the Hypervisor extension and timing channel protection, with an ultra-low-power multi-core RV32 cluster optimized for acceleration. This device is recognized as the first silicon prototype coupling RV64 and RV32 cores in a fully RISC-V host+accelerator architecture, achieving efficiency up to 1.8TOp/s/W.

Report

Key Highlights

• Target Device: Shaheen, a heterogeneous System-on-Chip (SoC) specifically designed for secure and autonomous navigation in ultra-low-power (ULP) nano-UAVs (sub-10cm drones).
• Architecture Novelty: Shaheen is cited as the first silicon prototype of a ULP SoC that couples a high-performance RV64 core and an accelerator RV32 cluster in a heterogeneous host+accelerator architecture based entirely on the RISC-V ISA.
• Security & OS Capability: The design overcomes limitations of state-of-the-art MCUs by supporting a Linux-capable OS environment and integrating advanced security features.
• Power/Area Footprint: Achieves an energy profile of 200mW consumption over a compact 9mm² area.

Technical Details

• Process Technology: Implemented in 22nm FDX technology.
• Host Core (RV64): Integrates a Linux-capable RV64 core.
  • Compliant with the v1.0 ratified RISC-V Hypervisor extension (H-extension).
  • Equipped with built-in timing channel protection.
• Memory Subsystem: Features a low-cost, low-power memory controller exposing up to 512MB of off-chip HyperRAM directly to the CPU.
• Accelerator Cluster (RV32): Includes a fully programmable, energy- and area-efficient multi-core cluster of RV32 cores.
  • Optimized for general-purpose Digital Signal Processing (DSP).
  • Optimized for reduced- and mixed-precision Machine Learning (ML) workloads.
• Performance Metrics (Cluster):
  • Peak Throughput: Up to 90GOp/s (on 2-bit integer kernels) and 7.9GFLOp/s (on 16-bit FP kernels).
  • Energy Efficiency: Up to 1.8TOp/s/W (on 2-bit integer kernels) and 150GFLOp/s/W (on 16-bit FP kernels).

Implications

• Validation of RISC-V Heterogeneity: This chip provides a critical real-world silicon demonstration that the open RISC-V ISA can seamlessly scale to handle both high-level, secure application processing (RV64, Linux, Hypervisor) and ultra-efficient parallel acceleration (RV32 ML clusters) within a single power-constrained platform.
• Advancing Secure Edge Computing: By integrating the ratified Hypervisor extension and timing channel protection, Shaheen enables the secure co-existence of general-purpose and real-time operating systems, a crucial requirement for reliable and secure autonomous systems like UAVs.
• Enabling Next-Gen Nano-UAVs: The high performance (90GOp/s) combined with extreme energy efficiency (1.8TOp/s/W) allows complex, real-time ML algorithms required for autonomy and navigation to run within the strict 200mW power budget of nano-UAVs, moving beyond simple bare-metal runtimes.