A First Look at RISC-V Virtualization from an Embedded Systems Perspective

Abstract

This article describes the first public implementation and evaluation of the RISC-V Hypervisor Extension (H-extension v0.6.1) targeting embedded and mixed-criticality systems on a Rocket chip core. The work successfully ported the Bao static partitioning hypervisor and introduced critical hardware enhancements, including an extended PLIC and enhanced timer infrastructure, to ensure low latency and avoid trap overheads. This open-sourced hardware implementation validates the H-extension specification and is currently being used by the RISC-V community toward its official ratification.

Report

Key Highlights

• First Public Implementation: Reports the initial public implementation and evaluation of the latest RISC-V H-extension specification (v0.6.1).
• Embedded Focus: The evaluation is specifically tailored for modern multi-core embedded and mixed-criticality systems.
• Hypervisor Port: Successfully ported Bao, an open-source static partitioning hypervisor, to the RISC-V architecture.
• Open Source Contribution: The resulting hardware implementation was open-sourced and is being used by the RISC-V community to support the ratification of the H-extension standard.
• Validated Deployment: Successfully deployed and tested the virtualized system on physical hardware (Zynq UltraScale+ MPSoC ZCU104).

Technical Details

• Specification Evaluated: RISC-V Hypervisor Extension (H-extension v0.6.1).
• Target Core: Rocket chip core.
• Hypervisor Used: Bao (static partitioning hypervisor).
• Interrupt Enhancement: Extended the RISC-V Platform-Level Interrupt Controller (PLIC) to enable direct guest interrupt injection, aiming for low and deterministic latency.
• Timing Optimization: Enhanced the timer infrastructure specifically to eliminate trap and emulation overheads.
• Evaluation Environments: Experiments were conducted using FireSim (a cycle-accurate, FPGA-accelerated simulator) and tested on the Zynq UltraScale+ MPSoC ZCU104 development board.

Implications

• Accelerated Ratification: The open-source implementation and practical validation provide crucial evidence required for the formal ratification of the RISC-V H-extension, moving the architecture closer to maturity.
• Enabling Critical Systems: By implementing a static partitioning hypervisor (Bao) and ensuring deterministic latency for interrupts, this work makes RISC-V a viable platform for high-reliability and mixed-criticality embedded systems (e.g., automotive or industrial control).
• Foundation for VM Ecosystem: This effort provides a reference implementation for future RISC-V hypervisor development, enabling complex operating system interactions and high-performance virtualization required by modern multi-core designs.
• Performance Baseline: The focus on avoiding trap and emulation overheads (especially concerning timers) establishes a performance baseline suitable for real-time applications in the embedded space.