A Classical Architecture For Digital Quantum Computers

Abstract

This paper presents a scalable classical control architecture for digital quantum computers, tackling major scaling bottlenecks by integrating a multi-core RISC-V CPU with in-house control electronics. The architecture features parallel quantum operation execution and a reconfigurable instruction set, uniquely reducing instruction transmission costs to constants independent of qubit scaling. Utilizing the RISC-V SoC for both control and complex classical computation (like syndrome decoding), the system demonstrates unprecedented surface code decoding capabilities up to distance 67 in just 1 microsecond.

Report

Key Highlights

• Scalable Control Solution: Introduces a classical architecture designed to cope simultaneously with numerous scaling challenges in digital quantum computers.
• RISC-V Integration: The system is fully implemented using a dedicated multi-core RISC-V CPU integrated with custom, in-house control electronics.
• Constant Overhead: The design fundamentally reduces instruction issuing and transmission costs to constants, meaning these costs do not scale with the growing number of qubits.
• CPU-Based Decoding: Syndrome decoding is handled by the general-purpose multi-core RISC-V CPU, replacing specialized decoding hardware and facilitating efficient load balancing.
• High Performance: Demonstrated rapid surface code workflow execution, achieving impressive decoding capabilities (up to distance 67) in $1 \text{\mu s}$.

Technical Details

• Architecture Type: Classical architecture for digital quantum computing control.
• Core Hardware: Multi-core RISC-V System-on-Chip (SoC) used for both qubit control and integrated classical computation (including decoding).
• Microarchitecture Features: Supports execution of quantum operations in parallel across arbitrary, predefined qubit groups.
• Instruction Set: Features a reconfigurable quantum instruction set, enabling easy qubit re-grouping and instruction extensions to accommodate evolving quantum hardware requirements.
• Decoding Implementation: Implements optimized decoding firmware (recent proposals) on the RISC-V SoC, parallelizing general inner decoders.
• Specific Decoders Used: In-house implementations of Union-Find and PyMatching 2.
• Decoding Capability (Benchmark): Achieves distance 47 (p=0.001) and distance 67 (p=0.0001) decoding performance within $1 \text{\mu s}$ on currently available SoCs.
• Demonstration: Implementation validated using the demanding surface code quantum computing workflow.

Implications

• Validation of RISC-V in Quantum Computing: This work firmly establishes the viability of standard, open-source RISC-V CPUs as the central processing unit for sophisticated quantum control stacks and error correction, potentially lowering hardware development barriers.
• Simplified Hybrid Systems: By moving computationally intensive tasks like syndrome decoding onto a general-purpose RISC-V core instead of specialized ASICs or FPGAs, the overall system design is simplified, improving maintainability and flexibility.
• Enhanced Scalability Model: The achieved constant instruction cost scaling removes a major physical bottleneck in scaling up qubit counts, making it easier for future quantum processors to exceed current size limitations without requiring proportional increases in classical control bandwidth.
• Ecosystem Flexibility: A reconfigurable instruction set built on a RISC-V platform allows the classical controller to easily adapt to different quantum hardware modalities (e.g., superconducting qubits, trapped ions) or new quantum error correction codes without costly hardware redesigns.