A 0.96pJ/SOP, 30.23K-neuron/mm^2 Heterogeneous Neuromorphic Chip With Fullerene-like Interconnection Topology for Edge-AI Computing

Abstract

This work introduces a heterogeneous neuromorphic system-on-chip (SoC) designed for highly efficient Edge-AI computing, achieving an impressive energy consumption of 0.96 pJ/SOP. The architecture integrates a tightly coupled RISC-V CPU and a neuromorphic processor utilizing a novel 'fullerene-like' interconnection topology for enhanced decentralized communication. Fabricated in 55 nm CMOS, the chip boasts a high neuron density of 30.23 K/mm² and a power density reduction of 67.5% compared to related works.

Report

Key Highlights

• Record Energy Efficiency: Achieves ultra-low energy efficiency of 0.96 pJ/SOP (Synaptic Operation).
• High Density: Features a high neuron density of 30.23 K-neuron/mm².
• Novel Topology: Utilizes a 'fullerene-like' Network-on-Chip (NoC) topology, significantly boosting node connectivity and decentralization.
• Low Power Footprint: Demonstrates a low power density of 0.52 mW/mm², resulting in a 67.5% reduction compared to existing architectures.
• Heterogeneous Integration: Tightly couples a standard RISC-V CPU with a specialized neuromorphic processor core on the same die.

Technical Details

• Fabrication Technology: The chip is fabricated using 55 nm CMOS technology.
• Die Specifications: The total die area is compact, measuring 5.42 mm².
• Neuromorphic Core Optimizations: Energy efficiency within the core is augmented through the implementation of sparse computing, partial membrane potential updates, and non-uniform weight quantization.
• Fullerene-like NoC: This novel topology, built from multiple neuromorphic cores and multi-mode routers, increases the average degree of communication nodes by 32% over traditional topologies, while maintaining a minimal degree variance of 0.93 for advanced decentralized communication.
• Scalability: The NoC design allows for straightforward scaling through the use of extended off-chip high-level router nodes.

Implications

• New Benchmarks for Edge-AI: The achieved energy efficiency (0.96 pJ/SOP) sets a highly competitive standard for neuromorphic processing, making complex AI tasks feasible in extremely power-constrained or battery-operated Edge-AI devices.
• Validation of RISC-V in Heterogeneous Systems: The successful tight coupling of the specialized neuromorphic processor with a RISC-V CPU reinforces RISC-V's viability and growing dominance as the flexible control plane (or GPP) necessary to manage and configure domain-specific accelerators.
• Advanced Architectural Design: The introduction of the 'fullerene-like' interconnection topology provides a crucial proof-of-concept for creating highly connected, robust, and decentralized communication fabrics, which are essential for scaling up future large-scale spiking neural networks (SNNs) and addressing communication bottlenecks in conventional grids.
• Area and Power Density Efficiency: Achieving high neuron density and dramatically reduced power density in a mature 55 nm process demonstrates that significant architectural innovations, rather than just process node scaling, can drive breakthroughs in hardware efficiency.