32-Bit RISC-V CPU Core on Logisim

Abstract

This project details the successful design and implementation of a 32-bit RISC-V CPU Core utilizing the Logisim digital logic simulation software. The effort capitalizes on the open-standard, royalty-free nature of the RISC-V Instruction Set Architecture (ISA), facilitating accessible hardware experimentation for designers and researchers. This model demonstrates a foundational core ideal for diverse applications, including embedded systems, IOT devices, and System-on-Chips (SOCs).

Report

Key Highlights

• Core Implementation: Focuses on developing a functional 32-Bit RISC-V CPU core.
• Platform Used: The entire core was designed and simulated within the Logisim software environment.
• Open Standard Focus: The project promotes the use of RISC-V specifically because it is an open standard ISA provided under licenses that require no usage fees.
• Target Audience: Aims to assist smaller device manufacturers, developers, and researchers by providing a proven, royalty-free architectural base.

Technical Details

• Architecture: RISC-V (Reduced Instruction Set Architecture).
• Core Specification: 32-Bit CPU Core.
• Methodology/Tooling: Design implemented entirely using Logisim, a software tool commonly used for visual simulation of digital circuits.
• ISA Definition: Based on established reduced instruction set computer (RISC) principles.
• Application Scope: Suitable for various embedded applications such as IOTs, embedded systems, disks, calculators, and custom SOCs.

Implications

• Educational and Prototyping Value: Utilizing Logisim makes the complex process of CPU architecture design highly visual and accessible, serving as an excellent educational tool for students and hobbyists.
• Driving RISC-V Adoption: By providing a readily demonstrable and open-source implementation, the project lowers the barrier to entry for developing RISC-V-based hardware.
• Fostering Innovation: The royalty-free nature of RISC-V, coupled with accessible design models like this one, encourages independent innovation among developers and researchers without the financial constraints associated with proprietary ISAs.
• Accessibility in Hardware: It supports the broader goal of democratizing hardware architecture, enabling small-scale manufacturers to build customized devices freely.